Comparator-type DC-DC converters are discussed in Japanese Laid-open Patent Publication Nos. 2004-104942 and 2007-174772, for example).
FIG. 1 illustrates a DC-DC converter 60 of related art. The DC-DC converter 60 includes a converter unit 61 and a control circuit 62. The converter unit 61 includes a transistor T1, a transistor T2, an inductor L1, and a capacitor C1
As illustrated in FIG. 1, a comparator 71 in the control circuit 62 compares an output voltage Vo with a reference voltage Vref, and outputs an output signal SG1 responsive to a level of the comparison results to a one-shot flipflop circuit 72.
If the output voltage Vo becomes lower than the reference voltage Vref, a high-level output signal S1 is output from the comparator 71 to the one-shot flipflop circuit 72. Upon receiving the high-level output signal S1 from the comparator 71, the one-shot flipflop circuit 72 is set, and outputs a high-level control signal DH from an output terminal Q for a specific period of time. In response to the high-level control signal DH, the transistor T1 is turned on and remains on for the specific period of time. After the high-level period of the control signal DH, the one-shot flipflop circuit 72 is reset, and outputs a low-level control signal DH. In response to the low-level control signal DH, the transistor T1 is turned off.
As illustrated in FIG. 2, the output voltage Vo rises in response to the on operation of the transistor T1 of FIG. 1. When the transistor T1 of FIG. 1 is turned off after an elapse of the specific time, energy stored on the inductor L1 of FIG. 1 is released. If the energy stored on the inductor L1 of FIG. 1 is reduced and causes the output voltage Vo to fall such that the output voltage Vo is lower than the reference voltage Vref, the one-shot flipflop circuit 72 of FIG. 1 outputs the control signal DH at a high level for a constant period of time and causes the transistor T1 of FIG. 1 to be on again for the constant period of time. Through the above-described operation, the output voltage Vo output from an output terminal Po of FIG. 1 is thus maintained as the reference voltage Vref as a voltage target.
Depending on an input voltage Vi and an equivalent series resistance (ESR) of the capacitor C1, a ripple voltage may be caused in the output voltage Vo output from the DC-DC converter 60 of FIG. 1.
As illustrated in FIG. 2, the ripple voltage may cause an error between an average value (denoted by a broken line) of the output voltage Vo and the reference voltage Vref as the voltage target.